IP Cores

Aliathon provides a wide range of FPGA/PLD based 'cores' for tele-communication and data-communication applications. Protocols such as SDH/SONET, E3/T3, ATM, POS and HDLC are catered for, in both single-channel and multi-channel options.
Aliathon's SONET/SDH IP Presentation...

Aliathon Cores	Description	Documentation
STM0/STM1/STM4 (OC1/OC3/OC12)	STM0/OC1, STM1/OC3, STM4/OC12 Framer, Deframer, Mapper and Demapper Cores. Available for both channelised and non-channelised applications, and including TUG3/TUG2 and TU processing, and PDH mapping/demapping functionality.	More details
OTU1 Framer/Deframer OTU1-FEC Encoder/Decoder	OTU-1 Framer/Deframer Cores running at 2.666 Gbps. OTU-1 RS Encoder/Decoder Core provides a very flexible, resource efficient FPGA based Core for G.709 Forward Error Correction (FEC) applications.	More details
E3/DS3	E3/DS3 Framer and Deframer cores - available for multi-channel applications (eg: multiple E3/DS3s carried over SDH) and single channel applications (eg: connection directly to an E3/DS3 LIU). Both single channel payloads (eg: ATM/PLCP) and channelised payloads (E1/DS1 over E2/G.747/DS2 over E3/DS3) are catered for.	More details
E2/DS2	E2/DS2 Framer and Deframer cores - available for multi-channel applications (eg: multiple E2/DS2s carried over SDH) and single channel applications.	More details
E1/T1	Multi-channel E1/T1 Framer and Deframer cores for connecting to Aliathon SDH and E3/DS3 cores and to multi-channel E1/T1 LIUs.	More details
E1/T1 Jitter Attenuator	Multi-channel E1/T1 Jitter Attnuator core for connecting to Aliathon SDH and E1/T1 core and to multi-channel E1/T1 LIUs.	More details
HDLC	Multi-channel HDLC Framer and Deframer cores, designed to connect to Aliathon's SDH and PDH cores	More details
ATM	Single-channel and multi-channel ATM Framers and Deframers, designed to connect to Aliathon's SDH, E3/T3 and E1/T1 cores.	More details
POS	Single-channel POS Framer and Deframer cores for use with Aliathon's SDH cores.	More details