Aliathon SDH/SONET Framer/Deframer Cores for STM16/OC48

General Description

Aliathon is pushing SDH/SONET IP into the 2.5Gbps, 10Gbps and 40Gbps arena. Current FPGA/PLD technology means that 2.5Gbps and 10Gbps are easily implemented in programmable devices, and this can compete against ASICs on cost, power and features.

Our intention is to present not such single-channel solutions (eg: POS and GFP over concatenated SDH/SONET payloads), but to extend our multi-channel capabilities into this area to offer high-speed, channelised solutions to the telecommunications industry.

Alithon STM16 Framer and Deframer Cores are currently being tested in Hardware and will be soon released.

The Aliathon STM16 Framer core provides a flexible, resource-efficient, programmable-logic based solution for SDH interfacing. It caters for both concatenated payloads, such as VC4-16c over STM16, and channelised applications, such as multiple VC3s over STM16. The core…

• Generates STM16 SONET/SDH.
• Scrambles the SDH frame, inserts Regenerator Section Overhead, and calculates B1 values.
• Inserts Multiplex Section Overhead and calculates B2 values.
• Generates all AU pointers (up to 48 for VC3 over STM16).
• Inserts VC3, VC4, VC4-4c and VC4-16c, both channelised and single-channel. All legal combinations
of VCs are supported. The VC settings may be dynamically reconfigured, and made on a per VC basis.
• Generates B3 values for all VCs and inserts Higher Order Path Overhead.

The Aliathon STM16 Deframer core provides a flexible, resource-efficient, programmable-logic based solution for SDH interfacing. It caters for both concatenated payloads, such as VC4-16c, and channelised applications, such as multiple VC3s over STM16. The core…

• Detects and aligns to the SDH framing pattern.
• Performs frame synchronisation for STM16, and generates LOS, OOF and LOF alarms.
• Descrambles the SDH frame, extracts Regenerator Section Overhead, and detects B1 errors.
• Extracts Multiplex Section Overhead and detects B2 errors.
• Processes all AU pointers.
• Extracts VC3, VC4, VC4-4c and VC4-16c, both channelised and single-channel. All legal
combinations of VCs are supported. The VC settings may be dynamically reconfigured, and
made on a per VC basis.
• Detects B3 errors for all VCs and extracts Higher Order Path Overhead.

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