Senior Staff

Steve McDonald

Steve founded Aliathon in April 2001 with Jed Martens and is Aliathon’s resident expert in Forward Error Correction as it relates to the Optical Transport Network.

Prior to founding Aliathon, Steve spent 3 years employed by Agilent Technologies in South Queensferry, Scotland, working in their Error Rate test group as an FPGA architect. During this time Steve designed FPGA systems that processed payloads up to and including OTU3 rates.

Before joining Agilent Technologies, Steve had a distinguished career in the high technology sector in Scotland, holding senior management positions with companies in the Security, Industrial and ePOS market places.

Jed Martens

Jed founded Aliathon in April 2001 with Steve McDonald and is Aliathon’s resident expert in the areas of channelized and unchannelized SONET/SDH and PDH systems.

Prior to founding Aliathon, Jed spent 2 years employed by Agilent Technologies in South Queensferry, Scotland, working in their channelized network analytics product group as an FPGA architect.

Jed is a native New Zealander, where he graduated with a First Class Honours Degree in Computing & Mathematical Sciences.  He also completed post-graduate research in the area of Passive Network Monitoring, as well as lecturing in Telecommunications Studies.

Ulises Hernandez

Ulises joined Aliathon in August 2003 as a Senior Design Engineer, since then he has been involved in the development of many successful FPGA based solutions for the telecommunications market working closely with many of our Tier 1/2/3 customers. Over these years he has acquired a very broad range of skills, both generic and specialist, in communication protocols, standards and encryption including OTN, SDH, SONET, PDH, ATM, AAL2/5, HDLC, GFP, POS, FEC and Ethernet.

Prior to joining Aliathon, Ulises worked at Hewlett-Packard/Agilent Technologies. Starting in 2000 as a research and development engineer, he was involved in developing the FPGA architecture of 155Mbps-10Gbps data communications test equipment.
Ulises was born in Logroño, Spain, in 1975 and holds a Master of Science degree with Honours in Electronics Engineering from University of Zaragoza. He also completed his Master Thesis in Zaragoza developing an state of the art FPGA based codec in 1999.

Alan McDade

Alan joined Aliathon in May 2010 having spent 15 years in the high tech semiconductor arena. He has responsibility for sales / new business development, marketing and operations.

Prior to joining Aliathon, Alan spent 10 years in the Altera Corporation European sales team. In this time, Alan served the company as a Snr. Field Applications Engineer (FAE) and most recently as FAE Manager for Northern Europe.
In this managerial position Alan lead his team to deliver year on year revenue and design commit growth for the company, outstripping regional targets and the industries compound annual growth predictions (CAGR) for FPGA technology.  He achieved this by delivering compelling & innovative solutions as well as a high quality of service to Altera's target customers which included some of the worlds largest telecommunications companies.

 

Mike MacGillis

Mike MacGillis joined Aliathon in July 2011 as an FPGA Design Engineer.

Prior to joining Aliathon, Mike worked as an ASIC/FPGA and Embedded software design engineer with a number of electronics companies in England and Scotland including Cadence Design Systems,  ARC Cores, STMicroelectronics and Aircraft Medical Ltd.  Mike is a Canadian who holds an Electrical Engineering Degree. He is currently working towards an MSc in Advanced Microelectronics.