Specialist FPGA solutions for OTN, SONET/SDH and PDH networks
Friday 24th May 2013
PDH
Overview
Aliathon’s PDH products support popular legacy PDH line rates, such as E1,T1, E3 and DS3.
The cores process multiple asynchronous paths and are available in channelized and non-channelized payload variants. This flexibility allows support for all types of PDH applications, such as Line Interfaces, Add/Drop Muxes and Circuit Emulation interfaces.
Please click on any of the products below for more info on our offering.
- Conforms to ITU G.704/ANSI T1.403.
- Performs frame synchronization and generation for T1, J1 and E1 PDH signals.
- Serial clk+data line interface support for connecting to standard E1/T1 LIUs.
- Jitter attenuation for up to 504/672 E1/T1 channels (2xOC12/STM4 links).
- Designed to provide G.832 and G.824 Output Jitter Compliance, for 2.048 kHz +/-50 ppm (E1), 1.544 kHz +/-32 ppm (T1).
E3/T3 LIU/Framer, contact us for product brief
- Conforms to ITU G.704/ANSI T1.403.
- Generates and performs frame synchronization for T3, J3 and E3 PDH signals.
- Supports up to 24 serial clk+data E3/T3 line interfaces.
- M13 (DS3->DS2-DS1) and E3->E2->E1 support.
